Intelligence Unleashed.
Intelligence that lives, infers, and learns in the physical world.
The single largest limit on AI economics isn't the math—it's the physics of moving data. Shuttling bits between storage and central GPU clusters consumes 90% of a chip's energy budget.
Sibacus licenses the Compute-in-Memory architecture that computes at the source. We build the compute brain directly inside memory cells, freeing AI from the cloud, the cooling fan, and the grid.
"The next wave of AI is physical AI. AI that understands the laws of physics, AI that can work among us."
Computes directly inside RRAM conductance arrays. By executing matrix arithmetic at the physical location of stored weights, we collapse the 20 pJ/bit data movement tax.
Shatters both the von Neumann memory wall and the thermodynamic dissipation wall. By computing at the source, we eliminate the physical data shuttling and heat generation that stall legacy compute.
Adjusts neural weights dynamically on-device via restricted binary updates. Enables continuous adaptation to local feedback loops with zero cloud telemetry.
Break the Thermodynamic Wall.
Binary-cell conductance shift architecture built for mature 22nm fabrication without $300M EUV tools.
Matrix arithmetic executes in-place inside RRAM arrays, bypassing DRAM weight fetch bottlenecks.
Fabricated on BEOL RRAM lines with >98% yields across standard high-volume silicon plants.
Binary CSD conductance states eliminate power-hungry ADCs/DACs and thermal calibration noise.
Intelligence Across 5 Physical Realms.
From low-Earth orbital constellations to precision agricultural soil sensors.
1W orbital compute modules for the EquaSat ASEAN sovereign satellite platform.
Autonomous drone vision & powerline inspection on sub-watt power budgets.
Self-navigating cargo in archipelagic ASEAN maritime corridors.
Edge vision and traffic telemetry without cloud backhaul latency.
Off-grid agricultural sensors & local soil chemistry diagnostics.
The 3-Horizon Roadmap.
Proven physics, validated emulation platforms, and a clear fabrication trajectory.
FPGA hardware emulation platforms, sky130 standard-cell validation, and initial 22nm BEOL RRAM IP core licensing.
Status: Active DevelopmentFine-tuned 135M–600M narrow models compiled directly to RRAM conductance arrays for sub-watt edge appliances.
Focus: Foundational DeploymentsVertical RRAM stacking drives tens-of-billions params per die; chiplet composition and non-volatile MoE dormancy extend that to frontier scale on mature nodes.
Goal: Edge-to-Frontier DensityWe Build the Brain Inside Physical AI.
Sibacus designs the compute architectures, IP cores, and compiler runtimes that power off-grid, physical edge intelligence. We license our silicon-abacus IP to foundries, OEMs, and sovereign technology partners worldwide.